InterSynth – Example-Driven Interconnect Synthesis

InterSynth is a command line tool implemented in C++ that generates (synthesizes) interconnects for heterogeneous coarse-grained reconfigurable logic circuits. Its input consists of descriptions of cells (only the interfaces, not the implementations) and example netlists utilizing this cells. These example netlists are then used by InterSynth to generate an interconnect that can implement the given example netlists and other circuits that are similar to these example netlists. This way it is possible to use InterSynth to create interconnects for a domain of applications using examples from this domain to describe it.

InterSynth can generate Verilog HDL files that implement the interconnect and instantiate the cells. It can also generate the configuration bit-streams for implementing netlists on a previously generated interconnect.


  • Example-Driven Interconnect Synthesis for Heterogeneous Coarse-Grain Reconfigurable Logic
    Clifford Wolf, Johann Glaser, Florian Schupfer, Jan Haase, Christoph Grimm
    download paper (pdf), download presentation (pdf) (as presented at FDL 2012)
  • InterSynth User Manual (preliminary version) by Clifford Wolf
    We are currently working on other parts of our coarse-grain design flow and will continue the work on the InterSynth manual later.
    download manual (pdf)

InterSynth is a tool for example-driven interconnect synthesis, typically used in the realm of digital circuit and system design. Interconnect synthesis refers to the process of generating the connections, or the „wiring,“ between different components within a hardware design. This process can be critical when dealing with complex systems such as FPGAs (Field Programmable Gate Arrays), ASICs (Application-Specific Integrated Circuits), or other custom integrated circuits where efficient data transfer between components is essential.

The example-driven aspect of InterSynth means that the tool uses examples or patterns from existing designs to inform and optimize the synthesis of interconnects in new projects. By leveraging this method, InterSynth can potentially predict the most effective ways to connect components based on proven design templates.

Features of InterSynth:

  • Pattern Matching: It can match existing interconnection patterns with current design requirements, facilitating reuse of tested and optimized design components.
  • Configuration: InterSynth might allow for customization to meet specific design constraints, such as size, speed, or power consumption.
  • Integration: This tool can be integrated into larger design workflows, potentially interfacing with other design and synthesis tools.

Applications of InterSynth:

  1. FPGA Design: For FPGA designers, InterSynth can be invaluable in planning the interconnects between different logic blocks, or between logic blocks and I/O pins, which is fundamental for implementing efficient digital designs on reconfigurable hardware.
  2. ASIC Layout: ASIC designers could utilize InterSynth in the floorplanning phase to devise efficient pathways for signals between various functional units of the chip to optimize performance and power consumption.
  3. Educational Purposes: Students learning about digital design and chip layout could benefit from InterSynth by observing how modifications to interconnects can impact the overall design metrics.
  4. Rapid Prototyping: Teams that need quick iterations on digital designs might use InterSynth to produce multiple interconnect schemas quickly, to evaluate the best design choices without manually routing each possibility.

Advantages of Using InterSynth:

  • Design Efficiency: Automated interconnect synthesis can result in more efficient use of hardware resources, lowering production costs, and improving performance.
  • Speed: It can accelerate the design process by automating what could be a very time-consuming manual task, especially in large or complex circuits.
  • Optimization: It provides the ability to optimize the design for various parameters, such as latency, throughput, or power usage.

Challenges and Limitations:

  • Complexity of Design: Complicated interconnects required for high-performance computing may be beyond the reach of automated tools, which may not fully understand all of the nuanced requirements of the system.
  • Adaptability: Example-driven methods might be limited by the range and quality of examples available, and may not always produce optimal results for novel design challenges.
  • Learning Curve: Engineers unfamiliar with example-driven synthesis tools might require additional time to familiarize themselves with the specifics of InterSynth's methodology and integration into their design process.

In conclusion, while the precise details of InterSynth's implementation and usage scenarios may vary depending on the version and specific application, the concept embodies a sophisticated approach to digital circuit design, using patterns from existing designs to inform and optimize new hardware interconnects. It represents the kind of tool that could significantly impact the efficiency and effectiveness of digital hardware design workflows.